DP 1.4 Link Layer CTS Testing

The selection of tests available for Unigraf's HBR3 capable DP 1.4 test device UCD-400 include all tests needed for DP 1.4 Link Layer CTS testing for DP Sinks and Sources.

EASY TO USE UCD CONSOLE GUI

UCD-Console is a common GUI for all UCD-300/400 series products. For DP 1.4. Link Layer CTS testing UCD Console features ready made test sets that you can easily select, run and monitor. Watch the video below to see how easily you can perform DP 1.4 Link Layer CTS tests on DisplayPort Sinks and Sources.

Available Tests for DP Sink and Source

Please refer to the table below to see what tests are available for DP 1.4 sink and source. For full coverage of Unigraf CTS Tests, please refer to:

DP 1.4 LL CTS for testing Source DUT

Test Reference Test Name
4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event
   
4.2.2.1 DPCD Receiver Capability and EDID Read upon HPD Plug Event
4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
4.2.2.3 EDID Read
4.2.2.4  EDID Read Failure #1: I2C-Over-AUX NACK
4.2.2.5  EDID Read Failure #2: I2C-Over-AUX DEFER
4.2.2.6  EDID Corruption Detection
4.2.2.7  Branch Device Detection upon HPD Plug Event
4.2.2.8  EDID Read on IRQ HPD Event after Branch Device Detection
4.2.2.9  E-DDC Four Block EDID Read
4.2.2.10  Link Status-Adjust Request AUX read interval during Link Training
   
4.3.1.1   Successful LT at All Supported Lane Counts and Link Speeds
4.3.1.2   Successful Link Training Upon HPD Plug Event
4.3.1.3   Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence
4.3.1.4   Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing
4.3.1.5  Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing
4.3.1.6   Successful LT with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence
4.3.1.7   Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence
4.3.1.8   Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing
4.3.1.9   Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing
4.3.1.10  Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]
4.3.1.11  Successful LT with Simultaneous Request for Differential Voltage Swing and Pre-emphasis during Clock Recovery Sequence
   
4.3.2.1   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock
4.3.2.2   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock
4.3.2.3   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock
4.3.2.4   Handling of IRQ HPD Pulse with No Error Status Bits Set
4.3.2.5   Lane Count Reduction
   
4.3.3.1   Video Time Stamp Generation
   
4.4.1.1  Data Packing and Steering
4.4.1.2  Main Stream Data Packing and Stuffing - Least Packed TU
4.4.1.3  Main Stream Data Packing and Stuffing - Most Packed TU
   
4.4.2  Main Video Stream Format Change Handling
   
4.4.3  Power Management

DP 1.4 LL CTS Additions for testing Source DUT

Test Reference Test Name
400.1.1 Source Device HPD Event Pulse Length Test
400.1.2 Source Device IRQ_HPD Pulse Length Test
400.1.3 Source Device Inactive HPD / Inactive AUX Test
400.2.1 Source Device Link Training CR Fallback Test
400.2.2 Source Device Link Training EQ Fallback Test

DP 1.4 LL CTS for testing Sink DUT

Test Reference Test Name
5.2.1.1  Read One Byte from Valid DPCD Address
5.2.1.2  DPCD Receiver Capability Read (Read 12 Bytes from Valid DPCD Address)
5.2.1.3  Write One Byte to Valid DPCD Address
5.2.1.4  Write Nine Bytes to Valid DPCD Addresses
5.2.1.5  Write EDID Offset (One Byte I2C-Over-AUX Write)
5.2.1.6  Read One EDID Byte (One Byte I2C-Over-AUX Read)
5.2.1.7  EDID Read (1 Byte I2C -Over-AUX Segment Write, 1 Byte I2C-Over-AUX Offset Write, 128 Byte I2C-Over-AUX Read)
5.2.1.8  Illegal AUX Request Syntax
5.2.1.9  Glitch Rejection
5.2.1.10  Interleaved EDID and DPCD Receiver Capability Read
5.2.1.11  Downstream Stop on MOT Reset
5.2.1.12  Downstream Stop on Timeout
   
5.2.2.1  Sink Organizationally Unique Identifier (OUI)
5.2.2.2  Sink Count
5.2.2.3  Sink Status
5.2.2.4  Sink Error Count
5.2.2.5  DPCD Address Range
5.2.2.6  Number of Receiver Ports
5.2.2.7  Main Link Channel Coding
5.2.2.8  ESI Field Mapping
   
5.3.1.1  Successful Link Training at All Supported Lane Counts and Link Speeds
5.3.1.2  Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence
5.3.1.3  Successful Link Training to a Lower Link Rate Due to Clock Recovery Lock Failure During Clock Recovery Sequence
5.3.1.4  Successful Link Training with Request of a Change to Pre-Emphasis and/or Voltage Swing Setting During Channel Equalization Sequence
5.3.1.5  Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence
5.3.1.6  Lane Count Reduction
5.3.1.7  Lane Count Increase

DP 1.4 LL CTS Additions for testing Sink DUT

Test Reference Test Name
500.1.1 2-Lane LT CR-EQ Fallback Test
500.1.2 1-Lane LT CR-EQ Fallback Test
500.1.3 Error Count Test