DP 1.4 a链路层兼容性测试

DP 1.4a 链路层兼容性测试

DP 1.4a链路层CTS测试

可测试HBR3 的DP 1.4测试设备UCD-400的测试选择包括DP1.4a链路层兼容性DP接收端和信号端所需的所有测试。

易于操控的UCD 图像式控制台(GUI)

UCD-Console是所有UCD-300/400系列产品的通用GUI。对于DP 1.4链路层兼容性测试UCD控制台具有现成的测试集,您可以轻松选择,运行和监控。 观看下面的视频,了解在DisplayPort接收端和信号端上执行DP 1.4 a链路层兼容性测试有多容易!

DP接收端和信号端的可用测试

请参阅下表,了解适用于DP 1.4接收端和信号端的测试。
有关Unigraf 兼容性测试的完整报道,请参阅:

Normative DP 1.4a LL CTS for testing Source DUT - Consolidated r1.1 draft 3

Test Reference Test Name
4.2.1.1 Source DUT Retry on No-Reply During AUX Read after HPD Plug Event
4.2.1.2 Source Retry on Invalid Reply During AUX Read after HPD Plug Event
4.2.1.3 Source Device HPD Event Pulse Length Test
4.2.1.4 Source Device IRQ_HPD Pulse Length Test
4.2.1.5 Source Device Inactive HPD / Inactive AUX Test
   
4.2.2.1 DPCD Receiver Capability and EDID Read upon HPD Plug Event
4.2.2.2 DPCD Receiver Capability Read upon HPD Plug Event
4.2.2.3 EDID Read
4.2.2.6 Source Device Inactive HPD / Inactive AUX Test
4.2.2.7 Branch Device Detection upon HPD Plug Event
4.2.2.8  EDID Read on IRQ HPD Event after Branch Device Detection
4.2.2.9 E-DDC Four Block EDID Read
4.2.2.10  Link Status-Adjust Request AUX read interval during Link Training
   
4.3.1.1   Successful LT at All Supported Lane Counts and Link Speeds
4.3.1.2   Successful Link Training Upon HPD Plug Event
4.3.1.3   Successful LT with Request of Higher Differential Voltage Swing During Clock Recovery Sequence
4.3.1.4   Successful LT to a Lower Link Rate #1: Iterate at Max Voltage Swing
4.3.1.5  Successful LT to a Lower Link Rate #2: Iterate at Minimum Voltage Swing
4.3.1.6   Successful LT with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence
4.3.1.7   Successful LT at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence
4.3.1.8   Unsuccessful LT at Lower Link Rate #1: Iterate at Max Voltage Swing
4.3.1.9   Unsuccessful LT at Lower Link Rate #2: Iterate at Minimum Voltage Swing
4.3.1.10  Unsuccessful LT due to Failure in Channel Equalization Sequence [loop count > 5]
4.3.1.11  Successful LT with Simultaneous Request for Differential Voltage Swing and Pre-emphasis during Clock Recovery Sequence
4.3.1.12 Source Device Link Training CR Fallback Test
4.3.1.13 Source Device Link Training EQ Fallback Test
   
4.3.2.1   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock
4.3.2.2   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock
4.3.2.3   Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock
4.3.2.4   Handling of IRQ HPD Pulse with No Error Status Bits Set
4.3.2.5   Lane Count Reduction
   
4.3.3.1 Video Time Stamp Generation
   
4.4.2 Main Video Stream Format Change Handling
4.4.3 Power Management
   
4.5.1.1 FEC enable verification for all supported Lane cound and Link Speed
4.5.1.2 FEC ready verification for non FEC capable sink

Informative DP 1.4a LL CTS for testing Source DUT - Under VESA review

Test Reference Test Name  
4.2.2.4 EDID Read Failure #1: I2C-Over-AUX NACK  
4.2.2.5 EDID Corruption Detection  
     
4.4.1.1 Data Packing and Steering  
4.4.1.2 Main Stream Data Packing and Stuffing - Least Packed TU  
4.4.1.3 Main Stream Data Packing and Stuffing - Most Packed TU  
     
4.4.4.1 Configuring Video and Audio Parameters  
4.4.4.2 Audio Stream Header Synchronization  
4.4.4.3 Audio Time Stamp Generation  
4.4.4.4 Audio InfoFrame Packet  
4.4.4.6 Audio Start Sequence  

Normative DP 1.4a LL CTS for testing Sink DUT - Consolidated r1.1 draft 3

Test Reference Test Name
5.2.1.1 Read One Byte from Valid DPCD Address
5.2.1.2 DPCD Receiver Capability Read (Read 12 Bytes from Valid DPCD Address)
5.2.1.3 Write One Byte to Valid DPCD Address
5.2.1.4 Write Nine Bytes to Valid DPCD Addresses
5.2.1.5  Write EDID Offset (One Byte I2C-Over-AUX Write)
5.2.1.6  Read One EDID Byte (One Byte I2C-Over-AUX Read)
5.2.1.7  EDID Read (1 Byte I2C -Over-AUX Segment Write, 1 Byte I2C-Over-AUX Offset Write, 128 Byte I2C-Over-AUX Read)
5.2.1.8  Illegal AUX Request Syntax
5.2.1.9  Glitch Rejection
5.2.1.10  Interleaved EDID and DPCD Receiver Capability Read
5.2.1.11  Downstream Stop on MOT Reset
5.2.1.12  Downstream Stop on Timeout
   
5.2.2.1  Sink Organizationally Unique Identifier (OUI)
5.2.2.2  Sink Count
5.2.2.3  Sink Status
5.2.2.4  Sink Error Count
5.2.2.5  DPCD Address Range
5.2.2.6  Number of Receiver Ports
5.2.2.7  Main Link Channel Coding
5.2.2.8  ESI Field Mapping
5.2.2.9 Sink Device Symbol Error Count 
   
5.3.1.1  Successful Link Training at All Supported Lane Counts and Link Speeds
5.3.1.2  Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence
5.3.1.3  Successful Link Training to a Lower Link Rate Due to Clock Recovery Lock Failure During Clock Recovery Sequence
5.3.1.4  Successful Link Training with Request of a Change to Pre-Emphasis and/or Voltage Swing Setting During Channel Equalization Sequence
5.3.1.5  Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence
5.3.1.6  Lane Count Reduction
5.3.1.7  Lane Count Increase
5.3.1.8 2-Lane Link Training CR/EQ Fallback Test
5.3.1.9 1-Lane Link Training CR/EQ Fallback Test
   
5.3.2.1 IRQ HPD Pulse Due to Loss of Symbol Lock and Clock Recovery Lock
5.3.2.2 IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock
   
5.5.1.1 Sink Device FEC capability verification
5.5.1.2 Succesful Link Training at All Supported Lane Counts and Link Rates with FEC Enable
5.5.1.3 Uncorrectable Block error count
5.5.1.4 Correctable Block error count
5.5.1.5 Correctable Bit error count
5.5.1.6 Correctable Parity Block error count
5.5.1.7 Correctable Parity Bit error count

Informative DP 1.4 LL CTS for testing Sink DUT - Under VESA review

Test Reference Test Name
5.4.1.1 Pixel Data Reconstruction
5.4.1.2 Main Stream Data Unpacking and Unstuffing – Least Packed TU
5.4.1.3 Main Stream Data Unpacking and Unstuffing – Most Packed TU
5.4.1.4 Pixel ClockRecovery
   
5.4.2 Main Video Stream Format Change Handling
   
5.4.3.1 Entering and Exiting Power Save Mode
5.4.3.2 Resumption of Main Link Activity After Extended Idle
   
5.4.4.1 Audio Test Patterns
5.4.4.2 Audio Startup and Format Change
5.4.4.3 RS Error Correction
5.4.4.4 Audio InfoFrame Packet
5.4.4.5 Audio Clock Recovery
5.4.4.6 Audio Stream Reception

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